vlsi-asic-fpga.blogspot.com

VLSI ASIC & FPGA

VLSI ASIC and FPGA. Wednesday, February 13, 2008. CDC - Clock Domain Crossing guidelines. A good article on CDC guidelines. Understanding Clock Domain Crossing Issues. Asynchronous signals in a synchronous world. Links to this post. Tuesday, January 29, 2008. Flip Flops and Register timings. The two important timings of a flip flop are. Links to this post. Divide by 3.5 clock divider. Divide by 3.5 clock divider. Divide by 3 first and add the negedge flop in series to make divide by 3.5. Divide by 3 = =.

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VLSI ASIC & FPGA | vlsi-asic-fpga.blogspot.com Reviews

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VLSI ASIC and FPGA. Wednesday, February 13, 2008. CDC - Clock Domain Crossing guidelines. A good article on CDC guidelines. Understanding Clock Domain Crossing Issues. Asynchronous signals in a synchronous world. Links to this post. Tuesday, January 29, 2008. Flip Flops and Register timings. The two important timings of a flip flop are. Links to this post. Divide by 3.5 clock divider. Divide by 3.5 clock divider. Divide by 3 first and add the negedge flop in series to make divide by 3.5. Divide by 3 = =.

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3 asic design fundamentals

4 soc clocking guidelines

5 handling async signals

6 synchronizer circuits

7 async issues

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VLSI ASIC & FPGA | vlsi-asic-fpga.blogspot.com Reviews

https://vlsi-asic-fpga.blogspot.com

VLSI ASIC and FPGA. Wednesday, February 13, 2008. CDC - Clock Domain Crossing guidelines. A good article on CDC guidelines. Understanding Clock Domain Crossing Issues. Asynchronous signals in a synchronous world. Links to this post. Tuesday, January 29, 2008. Flip Flops and Register timings. The two important timings of a flip flop are. Links to this post. Divide by 3.5 clock divider. Divide by 3.5 clock divider. Divide by 3 first and add the negedge flop in series to make divide by 3.5. Divide by 3 = =.

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vlsi-asic-fpga.blogspot.com

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VLSI ASIC & FPGA: February 2008

http://vlsi-asic-fpga.blogspot.com/2008_02_01_archive.html

VLSI ASIC and FPGA. Wednesday, February 13, 2008. CDC - Clock Domain Crossing guidelines. A good article on CDC guidelines. Understanding Clock Domain Crossing Issues. Asynchronous signals in a synchronous world. Links to this post. Subscribe to: Posts (Atom). View my complete profile.

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VLSI ASIC & FPGA: VLSI ASIC & FPGA

http://vlsi-asic-fpga.blogspot.com/2008/01/vlsi-asic-fpga.html

VLSI ASIC and FPGA. Thursday, January 17, 2008. VLSI ASIC and FPGA. VLSI basics and Knowledge. ASIC Design Verification fundamentals. Advantage of Virtex5 over Virtex4 FPGAs. Individual Block RAM Size. Virtex-5 - 36 Kbits, configurable as one 36 Kbits Block RAM or two independent 18 Kbits Block RAM. Virtex-4 -18 Kbits Block RAM. Number of Block RAM. Virtex5-550 MHz (-3 fast)/ 500 MHz (-2 medium). Virtex4-500 MHz (-12 fast). Page under construction. stay tuned for more updates on the ASIC and FPGA.

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VLSI ASIC & FPGA: VLSI Knowledge

http://vlsi-asic-fpga.blogspot.com/2008/01/vlsi-knowledge.html

VLSI ASIC and FPGA. Wednesday, January 23, 2008. Different types of flip flops. Conversion of one flip flop to other. Registers with Flip Flops (timing requirements). Divide by 3.5 clock divider. Adders, subtractors, multipliers, dividers. Subscribe to: Post Comments (Atom). VLSI ASIC and FPGA. Divide by 3.5 clock divider. Flip Flops and Register timings. View my complete profile.

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VLSI ASIC & FPGA: divide by 3.5 clock divider

http://vlsi-asic-fpga.blogspot.com/2008/01/divide-by-35-clock-divider.html

VLSI ASIC and FPGA. Tuesday, January 29, 2008. Divide by 3.5 clock divider. Divide by 3.5 clock divider. Divide by 3 first and add the negedge flop in series to make divide by 3.5. A simple divide by 3 counter can be as as follows. Divide by 3 = =. Always @ (posedge clk or negedge reset). The above code is a sequence of 00, 01, 10, 00. Assign divide by 3 = Q[0] Q0 inv ;. End of Divide by 3= =. Always @ (negedge clk). Assign divide by 3dot5 = divide by 3 divide by dot5;. End of Divide by 3.5= =.

5

VLSI ASIC & FPGA: SOURCE SYNCHRONOUS INTERFACES

http://vlsi-asic-fpga.blogspot.com/2008/01/source-synchronous-interfaces.html

VLSI ASIC and FPGA. Monday, January 28, 2008. Traditional interfaces limit interconnect speed to less than 250 MHz and pc-board-interconnect length to approximately 5 in. Designers are increasingly turning to source-synchronous interconnects that demonstrate transfer rates of 1 billion transitions/sec at distances of 5m and greater. For networking and I/O, examples include the scalable coherent interface (SCI), Silicon Graphics' ( http:/ www.sgi.com/. Synchronous interface Source-synchronous interface.

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VLSI ASIC & FPGA

VLSI ASIC and FPGA. Wednesday, February 13, 2008. CDC - Clock Domain Crossing guidelines. A good article on CDC guidelines. Understanding Clock Domain Crossing Issues. Asynchronous signals in a synchronous world. Links to this post. Tuesday, January 29, 2008. Flip Flops and Register timings. The two important timings of a flip flop are. Links to this post. Divide by 3.5 clock divider. Divide by 3.5 clock divider. Divide by 3 first and add the negedge flop in series to make divide by 3.5. Divide by 3 = =.

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